Career Profile
Yonghwi Kwon is currently a PhD student in School of Electrical Engineering, KAIST, Korea. Under supervision of Prof. Youngsoo Shin, his main research area is machine learning guided physical design, computational lithography, and low power design.
Education
MS & PhD integrated program
Projects
Dynamic voltage drop prediction with CNN (2019 - present)
Using U-net architecture, DvD of a layout is estimated with <15% error while it's >15x faster than conventional analysis.
Using U-net architecture, DvD of a layout is estimated with <15% error while it's >15x faster than conventional analysis.
Graph neural network guided leakage optimization (2019 - present)
GNN is adopted for faster Vth optimization on ECO stage for leakage power reduction without timing violation.
GNN is adopted for faster Vth optimization on ECO stage for leakage power reduction without timing violation.
Gate-level clock gating for cyclic logic paths (2019 - present)
Gating function of cyclic logic paths are identified to use as enable signals of clock gating cells.
Gating function of cyclic logic paths are identified to use as enable signals of clock gating cells.
RNN based OPC acceleration (2018 - present)
To reflect causality of segment correction process in MB-OPC, RNN is applied for accurate mask bias prediction.
To reflect causality of segment correction process in MB-OPC, RNN is applied for accurate mask bias prediction.
Synthetic test pattern generation using generative model (2018 - present)
To enhance the coverage of lithography model, synthetic patterns are generated using GANs.
To enhance the coverage of lithography model, synthetic patterns are generated using GANs.
Machine learning based SRAF printing prediction (2018 - 2019)
Project with SK Hynix R&D. ML-based SRAF printing prediction for full chip scale.
Project with SK Hynix R&D. ML-based SRAF printing prediction for full chip scale.
Early stage clock network power estimation (2017 - 2019)
Predicting clock network power with pre-CTS netlist and CTS parameters using ANN.
Predicting clock network power with pre-CTS netlist and CTS parameters using ANN.
Publications
SPIE Advanced Lithography, 2021
SPIE Advanced Lithography, 2021
SPIE Advanced Lithography, 2021
IEEE Transactions on Semiconductor Manufacturing (TSM)
ACM Great Lakes Symposium on VLSI (GLSVLSI), Aug. 2020
ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Sep. 2020
IEEE Transactions on Semiconductor Manufacturing (TSM), vol. 33, May 2020
SPIE Advanced Lithography, Feb. 2020
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2019
SPIE Advanced Lithography, Feb. 2019
IEEE International Symposium on Circuits and Systems (ISCAS), May 2018
Honors
Invited speaker @ Optical Society Korea (OSK) Summer Meeting
July 2020
July 2020
Excellence award @ SK Hynix Open Idea Contest
November 2019, awarded with ~18k$ funding.
November 2019, awarded with ~18k$ funding.
Invited speaker @ Next Generation Lithography (NGL) conf.
August 2019, presentation about BRNN-OPC.
August 2019, presentation about BRNN-OPC.
Richard Newton Young Fellow @ 56th Design Automation Conf. (DAC)
June 2019
June 2019
Volunteer Acitivty
Program management for 80 students and 12 mentors.
Bi-weekly teaching science and mathmatics to underpriviledged student group with talent on science. (Funded by Ministry of Science and ICT)